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vivado xsim xci compatibility. compatible with vivado synthesis.
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+106
-33
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5 files changed

+106
-33
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edalize/templates/xsim/Makefile.j2

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#Auto generated by Edalize jinja
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include config.mk
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all: xsim.dir/$(TARGET)/xsimk
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# {{ xci_list}}
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{%if xci_list %}
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xci.prj: xci.tcl
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vivado -mode batch -source xci.tcl
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cat $(TARGET).prj >> xci.prj
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xsim.dir/$(TARGET)/xsimk: $(SRC_FILES) xci.prj
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xelab $(TOPLEVEL) -prj xci.prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) -debug all
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{%else%}
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xsim.dir/$(TARGET)/xsimk: $(SRC_FILES)
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xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS) -debug all
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{%endif%}
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run: {{ default_run }}
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run-dflt: xsim.dir/$(TARGET)/xsimk
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xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
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run-vcd: xsim.dir/$(TARGET)/xsimk
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xsim -t vcd.tcl $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
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run-gui: xsim.dir/$(TARGET)/xsimk
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xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
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#Auto generated by Edalize
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TARGET = {{target}}
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TOPLEVEL = {{toplevel}}
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VLOG_DEFINES = {{vlog_defines}}
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VLOG_INCLUDES = {{vlog_includes}}
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GEN_PARAMS = {{gen_params}}
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XELAB_OPTIONS = {{xelab_options}}
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XSIM_OPTIONS = {{xsim_options}}
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SRC_FILES={{" ".join(src_list)}}

edalize/templates/xsim/xci.tcl.j2

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create_project -part {{xci_part}} myProject -force
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{% for n in xci_list %}
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read_ip {{ n }}
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{% endfor %}
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generate_target simulation [ get_files *.xci ]
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#export_simulation -force -simulator xsim -of_objects [get_files *.xci ]
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#get_files -all -of_objects [get_files *.xci]
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set f [get_files -compile_order sources -used_in simulation -of [get_files *.xci] -quiet]
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set fd [ open "xci.prj" "w" ]
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foreach d $f {
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puts $fd "verilog work $d"
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}
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close $fd

edalize/xsim.py

Lines changed: 50 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -12,42 +12,41 @@
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class Xsim(Edatool):
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"""
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Vivado Xsim backend
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* Standard design sources
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* IP: Supply the IP core xci file with file_type=xci and other files (like .prj) as file_type=user .
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you also have to specify xilinx part number in tools/xsim/part
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16-
argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"]
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MAKEFILE_TEMPLATE = """#Auto generated by Edalize
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include config.mk
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all: xsim.dir/$(TARGET)/xsimk
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xsim.dir/$(TARGET)/xsimk:
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xelab $(TOPLEVEL) -prj $(TARGET).prj -snapshot $(TARGET) $(VLOG_DEFINES) $(VLOG_INCLUDES) $(GEN_PARAMS) $(XELAB_OPTIONS)
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run: xsim.dir/$(TARGET)/xsimk
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xsim -R $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
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* you can also set tools/xsim/default_run to "run_vcd" in order to automatically generate vcd file during simulation
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"""
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run-gui: xsim.dir/$(TARGET)/xsimk
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xsim --gui $(XSIM_OPTIONS) $(TARGET) $(EXTRA_OPTIONS)
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"""
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CONFIG_MK_TEMPLATE = """#Auto generated by Edalize
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TARGET = {target}
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TOPLEVEL = {toplevel}
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argtypes = ["plusarg", "vlogdefine", "vlogparam", "generic"]
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37-
VLOG_DEFINES = {vlog_defines}
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VLOG_INCLUDES = {vlog_includes}
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GEN_PARAMS = {gen_params}
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41-
XELAB_OPTIONS = {xelab_options}
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XSIM_OPTIONS = {xsim_options}
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VCD_TCL = """#tcl script that runs simulation with vcd output
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open_vcd xsim_dump.vcd
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log_vcd *
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run all
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close_vcd
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quit
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"""
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@classmethod
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def get_doc(cls, api_ver):
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if api_ver == 0:
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return {
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"description": "XSim simulator from the Xilinx Vivado suite",
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"members": [
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{
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"name": "part",
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"type": "String",
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"desc": "xilinx part if using xci ip",
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},
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{
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"name": "default_run",
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"type": "String",
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"desc": "default target to run for makefile. use 'run-vcd' for automatic vcd generation",
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},
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{
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"name": "compilation_mode",
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"type": "String",
@@ -81,6 +80,8 @@ def _write_config_files(self):
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with open(os.path.join(self.work_root, self.name + ".prj"), "w") as f:
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mfcu = []
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(src_files, self.incdirs) = self._get_fileset_files()
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src_list = []
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xci_list = []
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for src_file in src_files:
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cmd = ""
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if src_file.file_type.startswith("verilogSource"):
@@ -96,10 +97,15 @@ def _write_config_files(self):
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cmd = "sv"
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elif src_file.file_type in ["user"]:
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pass
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elif src_file.file_type in ["data"]:
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os.system("ln -s %s %s"%(src_file.name, os.path.join(self.work_root, os.path.basename(src_file.name))));
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elif src_file.file_type in ["xci"]:
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xci_list.append(src_file.name)
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else:
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_s = "{} has unknown file type '{}'"
101106
logger.warning(_s.format(src_file.name, src_file.file_type))
102107
if cmd:
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src_list.append(src_file.name)
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if src_file.logical_name:
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lib = src_file.logical_name
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else:
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if mfc:
109115
f.write("sv work " + " ".join(mfcu))
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111-
with open(os.path.join(self.work_root, "config.mk"), "w") as f:
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if 1:
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vlog_defines = " ".join(
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[
114120
"--define {}={}".format(k, self._param_value_str(v))
@@ -135,20 +141,31 @@ def _write_config_files(self):
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xelab_options = " ".join(self.tool_options.get("xelab_options", []))
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xsim_options = " ".join(self.tool_options.get("xsim_options", []))
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138-
f.write(
139-
self.CONFIG_MK_TEMPLATE.format(
144+
if xci_list:
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xci_part = self.tool_options.get("part", "dflt_part")
146+
if xci_part == "dflt_part":
147+
logger.error("When using xci, you must define tools/xsim/part value")
148+
self.render_template("xci.tcl.j2", os.path.join(self.work_root, "xci.tcl"), dict(
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xci_list = xci_list,
150+
xci_part = xci_part
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))
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self.render_template("config.mk.j2", os.path.join(self.work_root, "config.mk"), dict(
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target=self.name,
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toplevel=self.toplevel,
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vlog_defines=vlog_defines,
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vlog_includes=vlog_includes,
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gen_params=gen_param_args,
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xelab_options=xelab_options,
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xsim_options=xsim_options,
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)
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)
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with open(os.path.join(self.work_root, "Makefile"), "w") as f:
151-
f.write(self.MAKEFILE_TEMPLATE)
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src_list=src_list,
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))
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self.render_template("Makefile.j2",os.path.join(self.work_root, "Makefile"),dict(
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default_run = self.tool_options.get("default_run", "run-dflt"),
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xci_list = xci_list
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))
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with open(os.path.join(self.work_root, "vcd.tcl"), "w") as f:
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f.write(self.VCD_TCL)
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def run_main(self):
154171
args = ["run"]

setup.py

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@@ -39,6 +39,9 @@ def read(fname):
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"templates/ghdl/Makefile.j2",
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"templates/openlane/openlane-makefile.j2",
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"templates/openlane/openlane-script-tcl.j2",
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"templates/xsim/config.mk.j2",
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"templates/xsim/Makefile.j2",
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"templates/xsim/xci.tcl.j2",
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],
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"edalize.tools": [
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"templates/yosys/edalize_yosys_procs.tcl.j2",

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