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libcontainer/intelrdt: add support for Schemata field
Implement support for the linux.intelRdt.schemata field of the spec. This allows management of the "schemata" file in the resctrl group in a generic way. Signed-off-by: Markus Lehtonen <[email protected]>
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4 files changed

+79
-15
lines changed

4 files changed

+79
-15
lines changed

libcontainer/configs/intelrdt.go

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,10 @@ type IntelRdt struct {
44
// The identity for RDT Class of Service
55
ClosID string `json:"closID,omitempty"`
66

7+
// The generic schemata
8+
// NOTE: Overrides hschemas specified in the L3CacheSchema and/or MemBwSchema
9+
Schemata []string `json:"memBwSchema,omitempty"`
10+
711
// The schema for L3 cache id and capacity bitmask (CBM)
812
// Format: "L3:<cache_id0>=<cbm0>;<cache_id1>=<cbm1>;..."
913
L3CacheSchema string `json:"l3_cache_schema,omitempty"`

libcontainer/intelrdt/intelrdt.go

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ func (m *Manager) Apply(pid int) (err error) {
458458
m.mu.Lock()
459459
defer m.mu.Unlock()
460460

461-
if m.config.IntelRdt.ClosID != "" && m.config.IntelRdt.L3CacheSchema == "" && m.config.IntelRdt.MemBwSchema == "" {
461+
if m.config.IntelRdt.ClosID != "" && m.config.IntelRdt.L3CacheSchema == "" && m.config.IntelRdt.MemBwSchema == "" && len(m.config.IntelRdt.Schemata) == 0 {
462462
// Check that the CLOS exists, i.e. it has been pre-configured to
463463
// conform with the runtime spec
464464
if _, err := os.Stat(path); err != nil {
@@ -647,23 +647,19 @@ func (m *Manager) Set(container *configs.Config) error {
647647
// the value written in does not necessarily match what gets read out
648648
// (leading zeros, cache id ordering etc).
649649

650-
// Write a single joint schema string to schemata file
651-
if l3CacheSchema != "" && memBwSchema != "" {
652-
if err := writeFile(path, "schemata", l3CacheSchema+"\n"+memBwSchema); err != nil {
653-
return err
654-
}
650+
parts := []string{}
651+
if l3CacheSchema != "" {
652+
parts = append(parts, l3CacheSchema)
655653
}
656-
657-
// Write only L3 cache schema string to schemata file
658-
if l3CacheSchema != "" && memBwSchema == "" {
659-
if err := writeFile(path, "schemata", l3CacheSchema); err != nil {
660-
return err
661-
}
654+
if memBwSchema != "" {
655+
parts = append(parts, memBwSchema)
662656
}
657+
parts = append(parts, container.IntelRdt.Schemata...)
663658

664-
// Write only memory bandwidth schema string to schemata file
665-
if l3CacheSchema == "" && memBwSchema != "" {
666-
if err := writeFile(path, "schemata", memBwSchema); err != nil {
659+
// Write a single joint schema string to schemata file
660+
schemata := strings.Join(parts, "\n")
661+
if schemata != "" {
662+
if err := writeFile(path, "schemata", schemata); err != nil {
667663
return err
668664
}
669665
}

libcontainer/intelrdt/intelrdt_test.go

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,69 @@ func TestIntelRdtSet(t *testing.T) {
3737
},
3838
schemataAfter: []string{"MB:0=9000;1=4000"},
3939
},
40+
{
41+
name: "L3 and MemBw",
42+
config: &configs.IntelRdt{
43+
L3CacheSchema: "L3:0=f0;1=f",
44+
MemBwSchema: "MB:0=9000;1=4000",
45+
},
46+
schemataAfter: []string{
47+
"L3:0=f0;1=f",
48+
"MB:0=9000;1=4000",
49+
},
50+
},
51+
{
52+
name: "Schemata",
53+
config: &configs.IntelRdt{
54+
Schemata: []string{
55+
"L3CODE:0=ff;1=ff",
56+
"L3DATA:0=f;1=f0",
57+
},
58+
},
59+
schemataAfter: []string{
60+
"L3CODE:0=ff;1=ff",
61+
"L3DATA:0=f;1=f0",
62+
},
63+
},
64+
{
65+
name: "Schemata and L3",
66+
config: &configs.IntelRdt{
67+
L3CacheSchema: "L3:0=f0;1=f",
68+
Schemata: []string{"L2:0=ff00;1=ff"},
69+
},
70+
schemataAfter: []string{
71+
"L3:0=f0;1=f",
72+
"L2:0=ff00;1=ff",
73+
},
74+
},
75+
{
76+
name: "Schemata and MemBw",
77+
config: &configs.IntelRdt{
78+
MemBwSchema: "MB:0=2000;1=4000",
79+
Schemata: []string{"L3:0=ff;1=ff"},
80+
},
81+
schemataAfter: []string{
82+
"MB:0=2000;1=4000",
83+
"L3:0=ff;1=ff",
84+
},
85+
},
86+
{
87+
name: "Schemata, L3 and MemBw",
88+
config: &configs.IntelRdt{
89+
L3CacheSchema: "L3:0=80;1=7f",
90+
MemBwSchema: "MB:0=2000;1=4000",
91+
Schemata: []string{
92+
"L2:0=ff00;1=ff",
93+
"L3:0=c0;1=3f",
94+
},
95+
},
96+
schemataAfter: []string{
97+
"L3:0=80;1=7f",
98+
"MB:0=2000;1=4000",
99+
"L2:0=ff00;1=ff",
100+
"L3:0=c0;1=3f",
101+
},
102+
},
40103
}
41104

42105
for _, tc := range tcs {

libcontainer/specconv/spec_linux.go

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -463,6 +463,7 @@ func CreateLibcontainerConfig(opts *CreateOpts) (*configs.Config, error) {
463463
if spec.Linux.IntelRdt != nil {
464464
config.IntelRdt = &configs.IntelRdt{
465465
ClosID: spec.Linux.IntelRdt.ClosID,
466+
Schemata: spec.Linux.IntelRdt.Schemata,
466467
L3CacheSchema: spec.Linux.IntelRdt.L3CacheSchema,
467468
MemBwSchema: spec.Linux.IntelRdt.MemBwSchema,
468469
}

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