Fix delayed assignment to class member

[wsnyder]

1. Fixes a delayed assignment to a class member. IEEE requires such assignments to be static.
2. Blacklist hdlconvertor_std2017_p753. Code is illegal; simple_bus is referenced but not defined

All simulators agree with this. Note Icarus does not support these tests for other reasons, but if I comment out the offending other code it agrees.

[github-actions]

Changes In Tests

Tool	New Failures	New Passes	Added	Removed	Not Affected
tree_sitter_verilog	2	0	0	1	4912
VeribleExtractor	0	0	0	1	4914
sv_parser	0	0	0	1	5005
moore	0	0	0	1	5005
Slang	0	0	0	1	5068
circt_verilog	0	0	0	1	5067
yosys_slang	0	0	0	0	4264
Slang_parse	0	0	0	1	5005
Odin	0	0	0	1	5005
tree_sitter_systemverilog	1	0	0	1	4910
SynligYosys	1	0	0	1	4725
Surelog	0	0	0	1	5068
Sv2v_zachjs	0	0	0	1	5068
moore_parse	0	0	0	1	4914
Icarus	0	0	0	1	5083
Yosys	0	0	0	1	4727
Verible	0	0	0	1	4914
Verilator	0	0	0	1	5083

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[wsnyder]

@kbieganski think is good to go. The new failures are random noise and unrelated. Verilator didn't get a pass with the change due to a general timeout issue I'll resolve separately.